Wireless communication applications have been a major driver in the development of high-speed high resolution analog-to-digital converters (ADC) with better alternating current (AC) performance in terms of signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR), as well as intermediate frequency (IF) sampling capability.
A major challenge in implementing such an ADC is preserving the high performance for high input frequencies. Generally, as the input frequency increases, the effect of input signal path nonlinearity becomes more detrimental to overall system performance. The detrimental impact of input signal path nonlinearity is especially true when large sampling capacitors, which are needed to achieve the high SNR requirement, are used.
Therefore a key to achieving high IF sampling performance is to create a low noise and low distortion input front-end capable of handling those high frequency signals. A buffer circuit plays a very critical role to achieve high linearity with IF sampling and to isolate the ADC's external driving network from the kick-back caused by the switching of the sampling capacitances.
FIG. 1 illustrates a buffer 100. Buffer 100 comprises a transistor 105, preferably a metal-oxide semiconductor field-effect transistor (MOSFET) device, arranged in a source follower configuration. Transistor 105 may be driven by a current source 110. Due to non-constant signal-dependent output impedance of a MOSFET device, buffer 100 often does not meet the high linearity requirements desired for many buffer circuit applications.